An IP Core and GUI for Implementing Multilayer Perceptron with a Fuzzy Activation Function on Configurable Logic Devices

Alfredo Rosado-Muñoz (University of Valencia, Spain)

Luis Gomez-Chova (University of Valencia, Spain)

Luis Gomez-Chova (University of Valencia, Spain)

Joan Vila Francés (University of Valencia, Spain)

Abstract: This paper describes the development of an Intellectual Property (IP) core in VHDL able to implement a Multilayer Perceptron (MLP) artificial neural network (ANN) topology with up to 2 hidden layers, 128 neurons, and 31 inputs per neuron. Neural network models are usually developed by using programming languages, such as Matlab®. However, their implementation in configurable logic hardware requires the use of some other tools and hardware description languages, such as as VHDL. For easy migration, a Matlab Graphical User Interface (GUI) to automatically translate the ANN architecture to VHDL code has been developed. In addition, the use of an activation function based on fuzzy logic for the implementation of the MLP neural network simplifies the logic and improves the results. The environment was tested using a typical prediction problem, the Mackey-Glass series, where several ANN topologies were generated, tested and implemented in an FPGA. Results show the excellent agreement between the results provided by the software model and the hardware implementation.

Keywords: FPGA, IP core, VHDL, configurable hardware, fuzzy logic, multilayer perceptron, neural networks, programmable logic

Categories: B.6.3, B.7.1, C.1.3, I.2.3