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Volume 13 / Issue 3

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DOI:   10.3217/jucs-013-03-0377


Design and Implementation of the AMCC Self-Timed Microprocessor in FPGAs

Susana Ortega-Cisneros (Universidad de Guadalajara, Mexico)

Juan Jóse Raygoza-Panduro (Universidad de Guadalajara, Mexico)

Alberto de la Mora Gálvez (Universidad de Guadalajara, Mexico)

Abstract: The development of processors with full custom technology has some disadvantages, such as the time used to design the processors and the cost of the implementation. In this article we used the programmable circuits FPGA such as an option of low cost for the development and implementation of Self-Timed (ST) systems. In addition it describes the architecture and the modules that compose the Asynchronous Microprocessor of Centralized Control (AMCC), and reviews the results of the occupation in the implementation of the FPGA. The operation of this processor only requires of an external pulse to the input of the first asynchronous control block, and with this pulse the sequence of request-recognition of the control unit begins, that it activates the cycle search and it begins the process of execution of the instructions, without the need of having a clock feeding the system. Once concluded the program, the microprocessor stops and include inherently the stoppable clock feature; i.e., circuit is stopped if it is not required (minimal dynamic consumption). Until it is activated again by an external request signal.

Keywords: 4 phase protocol, FPGA, Virtex II, asynchronous microprocessor, self-timed

Categories: B.1.0, B.2.1, B.6.0, C.1.1