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Articles by Topics
Topic B. - Hardware
Topic B.5 - REGISTER-TRANSFER-LEVEL IMPLEMENTATION
Topic B.5.1 - Design

P. Kornerup, D. W. Matula:
LCF: A Lexicographic Binary Representation of the Rationals
/jucs_1_7/lcf_a_lexicographic_binary
page 484 - 503
Vol.1 / Issue 7
W. Mayerwieser, K. C. Posch, R. Posch, V. Schindler:
Testing a High-Speed Data Path The Design of the RSAb Crypto Chip
/jucs_1_11/testing_a_high_speed
page 728 - 743
Vol.1 / Issue 11
M. del Carmen Peréz, J. Ureña, Á. Hernández, C. De Marziani, A. Jiménez, W.P. Marnane:
Hardware Implementation of an Efficient Correlator for Interleaved Complementary Sets of Sequences
/jucs_13_3/hardware_implementation_of_an
page 388 - 406
Vol.13 / Issue 3
J. Portilla, A. de Castro, E. de la Torre, T. Riesgo:
A Modular Architecture for Nodes in Wireless Sensor Networks
/jucs_12_3/a_modular_architecture_for
page 328 - 339
Vol.12 / Issue 3