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Volume 13 / Issue 3

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DOI:   10.3217/jucs-013-03-0407


A Dynamically and Partially Reconfigurable Implementation of the IDEA Algorithm Using FPGAs and Handel-C

José M. Granado-Criado (University of Extremadura, Spain)

Miguel A. Vega-Rodríguez (University of Extremadura, Spain)

Juan M. Sánchez-Pérez (University of Extremadura, Spain)

Juan A. Gómez-Pulido (University of Extremadura, Spain)

Abstract: Nowadays, the information security has achieved a great importance, both when information is sent through a non-secure network (as the Internet) and when data are stored in massive storage devices. The cryptographic algorithms are used in order to guarantee the security of data sent or stored. A lot of research is being done in order to improve the performance of the current cryptographic algorithms, including the use of FPGAs. In this work we present an implementation of the IDEA cryptographic algorithm using reconfigurable hardware (FPGAs). In addition, in order to improve the performance of the algorithm, partial and dynamic reconfiguration has been used to implement our final circuit. This fact allows us to obtain a very high encryption speed (14.757 Gb/s), getting better results than those found in the literature.

Keywords: FPGA, IDEA, cryptography, partial and dynamic reconfiguration

Categories: C.4, E.3