D. Drusinsky: On-line Monitoring of Metric Temporal Logic with Time-Series Constraints Using Alternating Finite Automata /jucs_12_5/on_line_monitoring_of
H. Hojjat, H. Nakhost, M. Sirjani: Integrating Module Checking and Deduction in a Formal Proof for the Perlman Spanning Tree Protocol (STP) /jucs_13_13/integrating_module_checking_and
S. Sasaki, T. Nishihara, D. Ando, M. Fujita: Hardware/Software Co-design and Verification Methodology from System Level Based on System Dependence Graph /jucs_13_13/hardware_software_codesign_and
H. Treseler, O. Stursberg, P. W. H. Chung, S. Yang: An Open Software Architecture for the Verification of Industrial Controllers /jucs_7_1/an_open_software_architecture
F. de Oliveira Jr., R. Lima, M. Cornelio, S. Soares, P. Maciel, R. Barreto, M. Oliveira Jr., E. Tavares: CML: C Modeling Language /jucs_13_6/cml_c_modeling_language