J.M. Granado-Criado, M.A. Vega-Rodríguez, J.M. Sánchez-Pérez, J.A. Gómez-Pulido: A Dynamically and Partially Reconfigurable Implementation of the IDEA Algorithm Using FPGAs and Handel-C /jucs_13_3/a_dynamically_and_partially
L. Nguyen, R. Safavi-Naini, K. Kurosawa: A Provably Secure and Efficient Verifiable Shuffle based on a Variant of the Paillier Cryptosystem /jucs_11_6/a_provably_secure_and
O. Pérez, Y. Berviller, C. Tanougast, S. Weber: The Use of Runtime Reconfiguration on FPGA Circuits to Increase the Performance of the AES Algorithm Implementation /jucs_13_3/the_use_of_runtime