Topic C.1.2 - Multiple Data Stream Architectures (Multiprocessors)

	J.M. Chaves-González, M.A. Vega-Rodríguez, J.A. Gómez-Pulido, J.M. Sánchez-Pérez: Pipeline-scheduling Simulator for Educational Purpose /jucs_13_7/pipeline_scheduling_simulator_for	page 959 - 969 Vol.13 / Issue 7
	L. Codrescu, D.S. Wills: On Dynamic Speculative Thread Partitioning and the MEM-Slicing Algorithm /jucs_6_10/on_dynamic_speculative_thread	page 908 - 927 Vol.6 / Issue 10
	P. Evripidou, C. Kyriacou: Data Driven Network Of Workstations (D²NOW) /jucs_6_10/data_driven_network_of	page 1015 - 1033 Vol.6 / Issue 10
	M. Forsell: MTAC - A Multithreaded VLIW Architecture for PRAM Simulation /jucs_3_9/mtac_a_multithreaded_vliw	page 1037 - 1055 Vol.3 / Issue 9
	K. Gopinath, M.K. Narasinhan: Performance of Switch Blocking on Multithreaded Architectures /jucs_6_10/performance_of_switch_blocking	page 928 - 947 Vol.6 / Issue 10
	D. J. Haglin, R. W. Ford: The Message-Minimizing Load Redistribution Problem /jucs_7_4/the_message_minimizing_load	page 291 - 306 Vol.7 / Issue 4
	K. Kavi, J. Arul, R. Giorgi: Execution and Cache Performance of the Scheduled Dataflow Architecture /jucs_6_10/execution_and_cache_performance	page 948 - 967 Vol.6 / Issue 10
	V. Leppaenen: On Implementing EREW Work-Optimally on Mesh of Trees /jucs_1_1/on_implementing_erew_work	page 23 - 34 Vol.1 / Issue 1
	V. Leppänen: Balanced PRAM Simulations via Moving Threads and Hashing /jucs_4_8/balanced_pram_simulations_via	page 675 - 689 Vol.4 / Issue 8
	C. Wallace, G. Tremblay, J. N. Amaral: An Abstract State Machine Specification and Verification of the Location Consistency Memory Model and Cache Protocol /jucs_7_11/an_abstract_state_machine	page 1088 - 1112 Vol.7 / Issue 11