Go home now Header Background Image
Search
Submission Procedure
share: |
 
Follow us
 
 
 
 
Articles by Topics
Topic B. - Hardware
Topic B.3 - MEMORY STRUCTURES
Topic B.3.3 - Performance Analysis and Design Aids

O. PĂ©rez, Y. Berviller, C. Tanougast, S. Weber:
The Use of Runtime Reconfiguration on FPGA Circuits to Increase the Performance of the AES Algorithm Implementation
/jucs_13_3/the_use_of_runtime
page 349 - 362
Vol.13 / Issue 3

Editors:
Tragoudas Spyros