The Price of Routing in FPGAs
Florent de Dinechin (Projet Arénaire, LIP-CNRS-INRIA, École Normale Superieure de Lyon, France)
Abstract: Studying the architectural evolution of mainstream field programmable gate arrays (FPGAs) leads to the following remark: in these circuits, the proportion of silicon devoted to reconfigurable routing is increasing, reducing the proportion of silicon available for computation resources. A quantitative analysis shows that this trend, if pursued, will lead to a widening gap between FPGA performance and VLSI performance. Some prospective solutions to this problem are discussed.
Keywords: FPGA, hardware complexity, reconfigurable computing, routing resources