Matrix Method to Detect Logic Hazards in Combinational Circuits with EX-OR Gates
E. C. Tan (Nanyang Technological University, Singapore)
M. H. Ho (Nanyang Technological University, Singapore)
Abstract: A matrix method is extended to include the detection of logic hazards in combinational logic circuits involving EX-OR gates. Essentially, the method generates 0- and 1-sets, or P- and S-sets, of all nodes in each gate level of a circuit progressively until it reaches the output of the circuit. The sets generated are subsequently used to determine the existence of static or dynamic hazards.
Keywords: exclusive-OR gates, hardware, logic hazards, matrix method