Dynamic Estimation of Temporary Failure in SoC FPGAs for Heterogeneous Applications
J. Kokila (National Institute of Technology, India)
N. Ramasubramanian (National Institute of Technology, India)
Ravindra Thamma (Central Connecticut State University, USA)
Abstract: Recent processors are shrinking in size due to the advancement of technology. Reliability is an important design parameter along with power, cost, and performance. The processors need to be fault tolerant to counter reliability challenges. This work proposes a dynamic thermal and voltage management (DTVM) system which ensures a reasonable level of fault tolerance. The fault tolerance system (FTS) identifies and subsequently can forecast temporary failures at run-time. The temporary failures are dynamically estimated on SoC FPGAs for a class of heterogeneous applications. The dynamic priority scheduling based on absolute deadline is adopted to improve the nature of FTS. Experimental results indicate that the failure rate reduces by 7.2% with the variation of 2% and 12% in temperature and voltage respectively.
Keywords: fault tolerance system, modified voltage lifetime model, physics of failure, priority dynamic scheduling algorithm, system on chip design
Categories: B.6.3, B.8.1, C.4, C.5, J.6