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Volume 14 / Issue 21

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DOI:   10.3217/jucs-014-21-3465


Instruction Scheduling Based on Subgraph Isomorphism for a High Performance Computer Processor

Ricardo Santos (Dom Bosco Catholic University, Brazil)

Rodolfo Azevedo (State University of Campina, Brazil)

Guido Araujo (State University of Campina, Brazil)

Abstract: This paper1 presents an instruction scheduling algorithm based on the Subgraph Isomorphism Problem. Given a Directed Acyclic Graph (DAG) G1, our algorithm looks for a subgraph G02 in a base graph G2, such that G02 is isomorphic to G1. The base graph G2 represents the arrangement of the processing elements of a high performance computer architecture named 2D-VLIW and G02 is the set of those processing elements required to execute operations in G1. We have compared this algorithm with a greedy list scheduling strategy using programs of the SPEC and MediaBench suites. In our experiments, the average Operation Per Cycle (OPC) and Operations Per Instruction (OPI) achieved by our algorithm are 1.45 and 1.40 times better than the OPC and OPI obtained by the list scheduling algorithm.

Keywords: 2D-VLIW, instruction scheduling, subgraph isomorphism

Categories: C.1.3, D.3.m, I.2.5