The Use of Runtime Reconfiguration on FPGA Circuits to Increase the Performance of the AES Algorithm Implementation
Oscar Pérez (Université Henri Poincaré I, France)
Yves Berviller (Université Henri Poincaré I, France)
Camel Tanougast (Université Henri Poincaré I, France)
Serge Weber (Université Henri Poincaré I, France)
Abstract: This article presents an architecture that encrypts data with the AES algorithm. This architecture can be implemented on the Xilinx Virtex II FPGA family, by applying pipelining and dynamic total reconfiguration (DTR). The originality of our implementation is that it computes sequentially in the FPGA the Key and Cipher part of the AES algorithm. This dynamic reconfiguration implementation allows a good optimization of logic resources with a high throughput. This architecture employs only 11619 slices allowing a considerable economy of the resources and reaching a maximum throughput of 44 Gbps.
Keywords: AES, FPGA, dynamic total reconfiguration, iterative looping, latency, pipeline, reconfiguration controller, reconfiguration time, registers, throughput, unrolling looping
Categories: B.2.2, B.3.3, B.4.4, D.4.8, E.3, E.4