Performance Evaluation and Limitations of a Vision System on a Reconfigurable/Programmable Chip
José Fernández-Pérez (Consejo Superior de Investigaciones Científicas (CSIC) and Universidad de Sevilla, Spain)
Francisco J. Sánchez-Fernández (Consejo Superior de Investigaciones Científicas (CSIC) and Universidad de Sevilla, Spain)
Ricardo Carmona-Galán (Consejo Superior de Investigaciones Científicas (CSIC) and Universidad de Sevilla, Spain)
Abstract: This paper presents a survey of the characteristics of a vision system implemented in a reconfigurable/programmable chip (FPGA). System limitations and performance have been evaluated in order to derive specifications and constraints for further vision system synthesis. The system hereby reported has a conventional architecture. It consists in a central microprocessor (CPU) and the necessary peripheral elements for data acquisition, data storage and communications. It has been designed to stand alone, but a link to the programming and debugging tools running in a digital host (PC) is provided. In order to alleviate the computational load of the central microprocessor, we have designed a visual co-processor in charge of the low-level image processing tasks. It operates autonomously, commanded by the CPU, as another system peripheral. The complete system, without the sensor, has been implemented in a single reconfigurable chip as a SOPC. The incorporation of a dedicated visual co-processor, with specific circuitry for low-level image processing acceleration, enhances the system throughput outperforming conventional processing schemes. However, time-multiplexing of the dedicated hardware remains a limiting factor for the achievable peak computing power. We have quantified this effect and sketched possible solutions, like replication of the specific image processing hardware.
Keywords: algorithms implemented in hardware, hardware architecture, image processing, implementation, system-on-a-programmable-chip
Categories: B.7.1, C.1.4, C.4, C.5.4, I.3.1, I.4.9